CPU Fetch-Decode-Execute Cycle Explained with Register Diagrams

How the Fetch-Decode-Execute Cycle Powers Modern Computing

When studying computer architecture, students often struggle to visualize how CPUs physically execute commands. After analyzing this foundational lesson, I've identified the core pain point: abstract explanations without concrete register visualization. The fetch-decode-execute cycle—Von Neumann's revolutionary stored-program concept—remains the engine of every digital device, from vintage machines like the 1948 Manchester Baby (1,100 instructions/second) to modern smartphones processing billions per second. This article bridges the gap between theoretical concepts and register-level operations using visual examples you won't find elsewhere.

Von Neumann Architecture Fundamentals

John Von Neumann's breakthrough was storing programs in main memory for sequential CPU processing. Unlike earlier computers requiring physical reconfiguration, his design introduced the program counter (PC) and memory address register (MAR) working in concert. The Manchester Baby demonstrated this in 1948 using RAM storing binary programs. Crucially, this architecture established three immutable principles:

• Instructions and data share the same memory
• Sequential instruction processing through fetching
• Binary execution through electronic circuits

Early computers used 16-bit registers, while modern CPUs utilize 64-bit or 128-bit registers. This exponential growth enables today's computational power, but the fundamental cycle remains unchanged. The video's assembly code example (LDA, ADD, STA) provides perfect context for visualizing register interactions.

Register Roles in the Execution Cycle

Program Counter and Instruction Handling

The PC holds the next instruction's memory address before current execution completes. During fetch phase:

1. PC copies address to MAR
2. MAR sends address via address bus (unidirectional)
3. Control Unit issues READ command
4. Instruction moves to Memory Data Register (MDR)
5. MDR transfers instruction to Current Instruction Register (CIR)

Critical nuance: The PC increments immediately after fetch, preparing for the next instruction. This pipelining enables continuous processing. Without this overlap, CPUs would idle between cycles.

Data Manipulation and Memory Interaction

When executing LDA 3 (Load Accumulator from address 3):

1. Control Unit decodes instruction, identifies memory access
2. Address "3" moves to MAR
3. READ command retrieves data (e.g., value 20)
4. Data travels via data bus (bidirectional) to MDR
5. MDR transfers value to Accumulator (ACC)

Arithmetic operations like ADD 4 involve the ALU:

• Memory value (e.g., 30) moves to MDR
• ALU adds MDR value to ACC contents
• Result stays in ACC for next operations

Store operations (STA 5) reverse the flow:

1. ACC value copies to MDR
2. Target address (5) loads into MAR
3. Control Unit issues WRITE command
4. MDR data transfers to specified memory location

Register Reference Table

Register	Purpose	Directionality
Program Counter (PC)	Stores next instruction address	CPU-internal
Memory Address Register (MAR)	Holds address for memory access	Output-only
Memory Data Register (MDR)	Temporary storage for data/instructions	Bidirectional
Current Instruction Register (CIR)	Holds instruction being decoded/executed	CPU-internal
Accumulator (ACC)	Stores arithmetic/logic results	CPU-internal

Modern Implications and Common Misconceptions

Beyond the Basic Cycle

While the video shows a simplified single-core model, modern processors add complexity:

• Pipelining: Simultaneous multi-stage execution (fetch next while decoding current)
• Multi-core processing: Parallel execution units
• Cache hierarchies: L1/L2/L3 caches reducing RAM access

Crucially, the core fetch-decode-execute sequence remains unchanged. The Manchester Mark 1's 1,100 instructions/second seems primitive next to modern billions, but both rely on identical register principles. This consistency is why understanding these fundamentals remains essential.

Debugging Assembly Code: 3-Step Checklist

When examining assembly instructions:

1. Trace register states: Document PC, MAR, MDR, ACC before/after each cycle
2. Verify bus activity: Confirm address bus (write-only) vs data bus (bidirectional)
3. Isolate memory access: Distinguish instruction fetch (read-only) from data read/write

Recommended Tools:

• MARS MIPS Simulator (free): Ideal for beginners with visual register tracking
• GDB Debugger (advanced): Industry-standard for low-level debugging
• Nandgame (web-based): Builds intuition through CPU construction

Key Takeaways and Interactive Practice

The fetch-decode-execute cycle transforms static memory contents into dynamic computation through synchronized register interactions. Von Neumann's architecture succeeded because it separated processing logic from storage—a design still governing every digital device today.

Test Your Understanding:

1. Why must the address bus be unidirectional while the data bus is bidirectional?
2. What happens to the Program Counter during a STORE operation?
3. How does pipelining improve upon the basic cycle?

Share which register interaction you find most challenging in the comments. Your real-world questions help shape future deep dives into CPU architecture!